Inside the Machine: An Illustrated Introduction to Microprocessors and Computer Architecture by jon stokes
Authors: jon stokes
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CPU, the
four phases of the instruction’s lifecycle take a total of 4 ns to complete. Therefore, you should set the duration of the CPU clock cycle to 4 ns, so that the
CPU can complete the instruction’s lifecycle—from fetch to write-back —in a single clock. (A CPU clock cycle is often just called a clock for short.) In Figure 3-6, the blue instruction leaves the code storage area, enters
the processor, and then advances through the phases of its lifecycle over the
course of the 4 ns clock period, until at the end of the fourth nanosecond, it
completes the last phase and its lifecycle is over. The end of the fourth nano-
second is also the end of the first clock cycle, so now that the first clock cycle is finished and the blue instruction has completed its execution, the red
instruction can enter the processor at the start of a new clock cycle and go
through the same process. This 4 ns sequence of steps is repeated until, after
a total of 16 ns (or four clock cycles), the processor has completed all four
instructions at a completion rate of 0.25 instructions/ns (= 4 instructions/
16 ns).
1ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns 9ns
Stored
Instructions
CPU
Fetch
Decode
Execute
Write
Completed
Instructions
Figure 3-6: A single-cycle processor
44
Chapter 3
Single-cycle processors like the one in Figure 3-6 are simple to design, but
they waste a lot of hardware resources. All of that white space in the diagram
represents processor hardware that’s sitting idle while it waits for the instruction that’s currently in the processor to finish executing. By pipelining the
processor in this figure, you can put more of that hardware to work every
nanosecond, thereby increasing the processor’s efficiency and its perfor-
mance on executing programs.
Before moving on, I should clarify a few concepts illustrated in Figure 3-6.
At the bottom is a region labeled “Completed Instructions.” Completed
instructions don’t actually go anywhere when they’re finished executing;
once they’ve done their job of telling the processor how to modify the
data stream, they’re simply deleted from the processor. So the “Completed
Instructions” box does not represent a real part of the computer, which
is why I’ve placed a dotted line around it. This area is just a place for you
to keep track of how many instructions the processor has completed in
a certain amount of time, or the processor’s instruction completion rate
(or completion rate , for short), so that when you compare different types of processors, you’ll have a place where you can quickly see which processor
performs better. The more instructions a processor completes in a set
amount of time, the better it performs on programs, which are an ordered
sequence of instructions. Think of the “Completed Instructions” box as a
sort of scoreboard for tracking each processor’s completion rate, and check
the box in each of the subsequent figures to see how long it takes for the
processor to populate this box.
Following on the preceding point, you may be curious as to why the
blue instruction that has completed in the fourth nanosecond does not
appear in the “Completed Instructions” box until the fifth nanosecond.
The reason is straightforward and stems from the nature of the diagram.
Because an instruction spends one complete nanosecond , from start to finish, in each stage of execution, the blue instruction enters the write phase at the
beginning of the fourth nanosecond and exits the write phase at the end of the fourth nanosecond. This means that the fifth nanosecond is the first
full nanosecond in which the blue instruction stands completed. Thus at
the beginning of the fifth nanosecond (which coincides with the end of the
fourth nanosecond), the processor has completed one instruction.
A Pipelined Processor
Pipelining a processor means breaking down its instruction execution
process—what I’ve been calling the
four phases of the instruction’s lifecycle take a total of 4 ns to complete. Therefore, you should set the duration of the CPU clock cycle to 4 ns, so that the
CPU can complete the instruction’s lifecycle—from fetch to write-back —in a single clock. (A CPU clock cycle is often just called a clock for short.) In Figure 3-6, the blue instruction leaves the code storage area, enters
the processor, and then advances through the phases of its lifecycle over the
course of the 4 ns clock period, until at the end of the fourth nanosecond, it
completes the last phase and its lifecycle is over. The end of the fourth nano-
second is also the end of the first clock cycle, so now that the first clock cycle is finished and the blue instruction has completed its execution, the red
instruction can enter the processor at the start of a new clock cycle and go
through the same process. This 4 ns sequence of steps is repeated until, after
a total of 16 ns (or four clock cycles), the processor has completed all four
instructions at a completion rate of 0.25 instructions/ns (= 4 instructions/
16 ns).
1ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns 9ns
Stored
Instructions
CPU
Fetch
Decode
Execute
Write
Completed
Instructions
Figure 3-6: A single-cycle processor
44
Chapter 3
Single-cycle processors like the one in Figure 3-6 are simple to design, but
they waste a lot of hardware resources. All of that white space in the diagram
represents processor hardware that’s sitting idle while it waits for the instruction that’s currently in the processor to finish executing. By pipelining the
processor in this figure, you can put more of that hardware to work every
nanosecond, thereby increasing the processor’s efficiency and its perfor-
mance on executing programs.
Before moving on, I should clarify a few concepts illustrated in Figure 3-6.
At the bottom is a region labeled “Completed Instructions.” Completed
instructions don’t actually go anywhere when they’re finished executing;
once they’ve done their job of telling the processor how to modify the
data stream, they’re simply deleted from the processor. So the “Completed
Instructions” box does not represent a real part of the computer, which
is why I’ve placed a dotted line around it. This area is just a place for you
to keep track of how many instructions the processor has completed in
a certain amount of time, or the processor’s instruction completion rate
(or completion rate , for short), so that when you compare different types of processors, you’ll have a place where you can quickly see which processor
performs better. The more instructions a processor completes in a set
amount of time, the better it performs on programs, which are an ordered
sequence of instructions. Think of the “Completed Instructions” box as a
sort of scoreboard for tracking each processor’s completion rate, and check
the box in each of the subsequent figures to see how long it takes for the
processor to populate this box.
Following on the preceding point, you may be curious as to why the
blue instruction that has completed in the fourth nanosecond does not
appear in the “Completed Instructions” box until the fifth nanosecond.
The reason is straightforward and stems from the nature of the diagram.
Because an instruction spends one complete nanosecond , from start to finish, in each stage of execution, the blue instruction enters the write phase at the
beginning of the fourth nanosecond and exits the write phase at the end of the fourth nanosecond. This means that the fifth nanosecond is the first
full nanosecond in which the blue instruction stands completed. Thus at
the beginning of the fifth nanosecond (which coincides with the end of the
fourth nanosecond), the processor has completed one instruction.
A Pipelined Processor
Pipelining a processor means breaking down its instruction execution
process—what I’ve been calling the
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